Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
FIG. 1 illustrates a block diagram for a basic flyback converter 100. The flyback converter 100 converts the voltage level of a DC input (e.g., Vin) to new voltage level Vout in order to drive a load. The flyback converter 100 comprises a transformer T having a primary winding and a secondary winding. An input voltage Vin is applied to input terminals 102 of the primary winding. The other terminal of the primary winding is connected to a switch Q (e.g., Metal Oxide Semiconductor Field Effect Transistor, MOSFET). A diode D is connected in series between a terminal of the secondary winding and an output terminal 104 of the flyback converter 100 (note the relation of the dotted ends of the primary and secondary windings, where by convention current enters). A capacitor C is connected between output terminal 104 and 106.
When the switch Q is switched ON (closed), an input current IP from the DC input flows through the primary winding of the transformer T, creating a magnetic field in the transformer core and inducing a voltage in the secondary winding. At this time, the diode D is reverse biased (the dotted end is at a higher potential than the other terminal) and so no current flows through the secondary winding (IS=0).
When switch Q is switched OFF (opened) after some time, the current path in the primary winding is broken (IP=0). The magnetic field collapses causing a voltage reversal to occur in the primary and secondary windings. The reversal in voltage polarity in the secondary winding results in the diode D being forward biased, resulting in the flow of current IS. The current IS charges capacitor C, causing Vout to increase from 0V. When the capacitor C is charged, a current flow IC from the capacitor can drive a load connected across the output terminals 104 and 106.
A feedback path 108 from the output Vout may be used to control a duty cycle (e.g., the ON time of a switching cycle expressed as a percentage of the period of the switching cycle) of the switching control signal in order to vary the currents IP and IS in order to maintain a charge the capacitor C to maintain a desired voltage level for Vout. At power up, however, Vout increases from an initial voltage level of 0V. Accordingly, the feedback path 108 may not be able to provide an adequate feedback signal to properly control the ON and OFF times for switch Q. Depending on the startup sequence used to initially charge the capacitor C, the transformer T may be driven into saturation during the startup sequence. Driving the transformer T into saturation can result in sufficiently high voltage levels across the switch Q (e.g., drain-source voltage VDS in a MOSFET) as to damage the switch. A solution is to use sufficiently large transformer that has a higher saturation rating. However, such devices are generally expensive, and more critically, may be too large for a given design. Likewise, a sufficiently robust MOSFET device having a high voltage rating may be too large for a given design and/or too expensive to use.